1. Field
The following description relates to a memory programming method and apparatus, and to a multi-bit programming method for a one-time programmable memory and apparatus.
2. Description of Related Art
A one time programmable (OTP) memory includes a plurality of OTP unit cells, the cells being arranged in row and column directions.
The OTP unit cell is formed in a volatile or nonvolatile memory element such as a dynamic random-access memory (DRAM), an electrically erasable programmable read-only memory (EEPROM) or a FLASH to be used for a memory repair. In addition, in a mixed-signal chip mixing an analog chip and a digital chip, the OTP unit cell is used for trimming an inner operating voltage and a frequency.
In general, the OTP unit cell includes an anti-fuse formed of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, hereinafter, referred to as an MOS transistor) and at least one MOS transistor. The OTP unit cell is formed of a single or an array in each of memory, thereby being used in the repair or trimming.
The Korean Registration Patent No. 10-0845407 (Jul. 3, 2008) relates to a one-time-programmable cell and a OTP memory having the same, implementing fewer MOS transistor so that it may have a smaller area and a shorter access time, and having an inverter type sense amplifier so that it may be possible to reduce leakage current and area.
The Korean Registration Patent No. 10-1051673 (Jul. 19, 2011) relates to an anti-fuse, a forming method thereof, and a unit cell of a nonvolatile memory device having the same, capable of causing a stable breakdown of a gate dielectric layer of the anti-fuse formed of a MOS transistor, so that a data sensing margin during a reading operation is improved and then an operation reliability may be enhanced.
FIG. 1 is a cross-sectional diagram illustrating an OTP memory programming method in conventional art. Referring to FIG. 1, the OTP memory programming scheme is performed by providing a high voltage (i.e., OTPV) to an anti-fuse (e.g., CMOS anti-fuse) of an OTP unit cell 100 and breaking a CMOS gate insulating layer (e.g., Gate Oxide) 103 to decrease a resistance value between a gate 104 and a substrate 101 to a specific resistance value (e.g., several M Ohm).
The anti-fuse of the OTP unit cell 100 includes a gate electrode 104 formed on the substrate 101, the junction area 105 formed in the substrate that is exposed to a side wall direction of the gate electrode 104 and the gate insulating layer 103 formed between the gate electrode 104 and the substrate 101 in a comparatively thin thickness.
The junction area 105 and a pick-up area 106 (i.e., an area providing a bias to a well 102) are interconnected with each other, and are connected with a ground voltage terminal VSS. Further, a writing voltage OTPV is provided to the gate electrode 104 through a metal wiring. Therefore, a high electric field is formed between the gate electrode 104 and the substrate 101 to break the gate insulating layer 103 and to electrically short the gate electrode 104 and the substrate 101.
The OTP memory programming scheme in the art includes writing data, reading data written on the OTP memory and comparing the written data with data to be written. Also, the OTP memory programming scheme in the art repeatedly performs those procedures until a test of all bits in the OTP memory passes (i.e., the written data matches up with the data to be written). For example, when a writing procedure is performed on 8-bit unit cells of the OTP memory, if the test of all of 8-bit data in the OTP memory does not pass, then a re-writing procedure is performed again on all of the 8-bit data.
High current energy is concentrated on a path in which gate insulating layer was broken so that energy concentration is comparatively reduced for the unit cell whose gate insulating layer was not broken. Therefore, the writing procedure takes long time and a yield rate is reduced because a breaking of the insulating layer is not properly performed.